1. Field of the Invention
This invention generally relates to computer-aided design of electronic circuits, and more specifically, the invention relates to constructing corner models for multiple performance targets.
2. Background Art
Computer aids for electronic circuit designers are becoming more and more popular. Examples of these computer aids include electronic circuit simulators such as the Simulation Program with Integrated Circuit Emphasis (SPICE) developed at the University of California, Berkeley (UC Berkeley), and various enhanced versions or derivatives of SPICE, such as, SPICE2 or SPICE3, HSPICE, PSPICE, and SPECTRE.
An electronic circuit may contain circuit elements such as resistors, capacitors, inductors, mutual inductors, transmission lines, diodes, bipolar junction transistors (BJT), junction field effect transistors (JFET), and metal-on-silicon field effect transistors (MOSFET), etc. A SPICE circuit simulator is a program that simulates the performance of electronic circuits. SPICE solves sets of non-linear differential equations in the frequency domain, steady state and time domain and can simulate the behavior of transistor and gate designs. In SPICE, a circuit is handled in a node/element fashion, i.e., the circuit is regarded as a collection of various elements (transistors, resistors, capacitors, etc.) and the elements are connected at nodes. Thus, each element must be modeled in order to simulate the entire circuit. Most SPICE circuit simulators have built in models for modeling semiconductor devices, and are set up so that the user need only specify model parameter values associated with the models.
Whether it is built-in or plug-in, a device model for a SPICE circuit simulator typically includes model equations and a set of model parameters, which are used to mathematically represent device characteristics of a device element under various bias conditions. For example, for a MOSFET device model, in DC and AC analysis, the inputs of the device model are the drain-to-source, gate-to-source, bulk-to-source voltages, and the device temperature, and the outputs are the various terminal currents. Therefore, the model parameters, along with the model equations in the device model, directly affect the final outcome of the terminal currents.
Compact/Spice models typically support Monte Carlo simulations. To reduce simulation time, however, it is desirable to also have a corner model. The corner model refers to a model wherein some of the varying electrical characteristics of a device show a lower frequency of occurrence than statistical typical values (average values, median values and the like) are expressed as corners, which define the limits of the variations. At the corners, to what extent the variations in model parameters and process parameters are tolerated is calculated.
Often it is desirable to find a common corner for multiple performance targets. For example, in FET corner models, a corner to meet both drain current and threshold voltage corner conditions at both short and long channel lengths. In a corner model aimed at circuit performance targets, it is desirable to have a common corner model for multiple logic gates, like ring oscillator, NAND, NOR, etc.
In another example, there are N1 logic circuits/standard cells and, for each one, there is a 3-σ maximum delay requirement and a 3-σ maximum power/leakage requirement. We want to build a set of corner models to satisfy a total of N=2N1 requirements. This can be done by (i) building N separate corner models (one corner model to cover one corner), (ii) building one common corner model to cover all N corners, or (iii) building J(1<J<N) corner models (1st corner model covers n1 corners, 2nd corner model covers another n2 corners, . . . , n1+n2+ . . . +nJ=N). If successful and acceptable, (ii) is the most desirable solution and (i) is the least desirable solution. However, for (ii), there may not be a proper solution for such a common corner. Or, if there is a common corner, its probability can be too small. So the problem here is: How to decide how many corner models are needed in the suite of corner solution. Important considerations are, for each corner model in the suite of corner solution which of several performance corners to cover, and what criteria should be used to make such a decision.
In yet another example involving delay difference among different logic circuits (or among different paths), there are I logic circuits/standard cells and, for each one, there are both 3-σ maximum delay requirement and a 3-σ minimum delay requirement. We want to build a set of corner models to cover a total of N=2I performance corners. In such an example, we have the freedom to choose the combinations of one circuit's maximum delay corner with another circuit's either maximum or minimum delay corner and build a common corner model to satisfy the chosen corners simultaneously. This can be done by (i) building N separate corner models (one corner model to cover one corner), or (ii) building J(1<J<N) corner models (1st corner model covers n1 corners, 2nd corner model covers another n2 corners, . . . , n1+n2+ . . . +nJ=N). If successful and acceptable, the smaller the number (J) of the corner model is, the better the corner solution is. Again, the problem here is: How to decide how many corner models are needed in the suite of corner solution. Important issues are, for each corner model in the suite of corner solution, how do we choose a proper combination among maximum and minimum performance corners, and what criteria should be used to make such a decision.